CIC filters deployed to date are frequently used in digital down-converter applications, as they permit a more efficient hardware implementation than alternate finite-impulse response filters with decimation or a conventional averaging technique. If constrained to powers-of-two decimation values, the CIC can be implemented without multiply or divide operations, but must use very large bit width adders and accumulators for the large values of decimation or interpolation often required in current digital filtering applications.
The problem with the current approach is the granularity of the selectable output sample rate. As an example, consider a CIC filter with powers-of two decimation values from 8 to 16,384 (23 to 214). Thus, if the input sample rate is, for example, 16 MHz, the discrete output sample rates available are 2 MHz, 1 MHz, 500 KHz, . . . 3.91 KHz, 1.95 KHz, and 0.98 KHz. Since the output sample rate of the CIC is typically input to a digital filter, and to minimize the number of taps required for these follow-on filters, it is highly desirable to improve the granularity of the R values. As an example, an FIR filter with a sharp cutoff frequency at 250 KHz would, with powers-of-two decimation, require a sample rate of 1 MHz and require 507 taps to achieve 80 dB of attenuation with less than 1 dB of ripple. If integer R values were available, the sample rate could be set at 516 KHz (R=31) and the filter would require only 235 taps, improving filter latency and processing throughput and power requirements.